As generally known in the art, semiconductor packages have been developed to have a compact size while improving various electrical characteristics thereof. A representative example of the semiconductor package is a so-called BGA (ball grid array) package. As is known to those of ordinary skill in the art, a BGA package has a size similar to that of a semiconductor chip, so that the mounting space for the BGA package can be minimized. In addition, since the BGA package is electrically connected to external circuits through one or more solder balls on the BGA package, the transmission path between the BGA package solder ball and a semiconductor chip inside the package is kept as short as possible, so that the electrical characteristics of the BGA package can be improved.
Recently, an FBGA (fine-pitch BGA) package has been suggested. The FBGA package not only has the advantages of the BGA package, but also realizes a fine pitch or close spacing of solder balls used for a signal/power input/output pins and is suitable for highly integrated semiconductor devices. FIG. 1 shows a representation of the structure of a typical FBGA package.
As shown in FIG. 1, a conventional BOC (Board On Chip) type FBGA package includes a center pad type semiconductor chip 11 bonded to a substrate 15 having a window by means of an adhesive 13 and provided at a lower portion thereof with a bonding pad 12. In addition, the bonding pad 12 of the semiconductor chip 11, which is exposed through the window of the substrate 15, is connected to a bond finger (not shown) of the substrate 15 through a bonding wire 16. An upper surface of the substrate 15 including the semiconductor chip 11 and the window part of the substrate 15 including the bonding wire 16 are sealed by means of a sealing material 17, such as EMC (epoxy molding compound). In addition, solder balls 18, which are used for mounting the FBGA package on an external circuit, are attached to a ball land (not shown) formed at a lower surface of the substrate 15.
However, according to the above BOC type FBGA package, the window must be formed at the center portion of the substrate so as to wire-bond the bonding pad of the semiconductor chip to the bond finger of the substrate, so that the manufacturing cost for the substrate may increase as compared with that of the substrate, which does not require the window, thereby increasing the manufacturing cost for the BOC type FBGA package. In addition, since only one semiconductor chip is accommodated in the BOC type FBGA package, it is difficult to increase the capacity of the BOC type FBGA package.
In order to increase the capacity of the semiconductor package, as shown in FIG. 2, a chip stack package has been suggested. The chip stack package has a structure similar to that of the above BOC type FBGA package, except that it can theoretically accommodate two semiconductor chips therein but as a practical matter, such a chip stack package requires a bonding wire 26b having a very long length in order to electrically connect an upper semiconductor chip 24 with a substrate 25. As can be seen in FIG. 2, the bonding wire 26b is long and can be easily broken during a packaging molding process. In particular, since transmission paths of electric signals between a lower semiconductor chip 21 and the upper semiconductor chip 24, are different from each other, that is, the lengths of bonding wires 26a and 26b are different from each other, the signal transmission characteristics, such as propagation delays will be different and the operation of the semiconductor chips can be degraded. In addition, if bonding pads are aligned in a dual array structure, it is difficult to variously design the substrate relative to the stack, making it difficult to apply the semiconductor package to a high-speed product.
In FIG. 2, reference numerals 23, 27 and 28 represent an adhesive, a sealing material and solder balls, respectively.
FIG. 3 is a sectional view illustrating a conventional planar stack package. As shown in FIG. 3, the conventional planar stack package includes semiconductor chips 31 and 34 aligned on a substrate 35 in parallel to each other while being sealed by means of a sealing material. Such a planar stack package can be easily fabricated and can improve the signal transmission characteristics because the transmission path for the electric signal between the semiconductor chips 31 and 34 and the substrate 35 can be uniformly established. In addition, since bonding wires 36a and 36b have relatively short lengths, the bonding wires 36a and 36b can be prevented from being broken during the molding process.
However, although the above planar stack package is suitable for edge pad type chips, it is not suitable for center pad type chips. In addition, if the size of the semiconductor chip is enlarged, it is difficult to fabricate the planar stack package. That is, if the size of the semiconductor chip is enlarged, the planar stack package must be fabricated while increasing the size of the substrate corresponding to the size of the semiconductor chip. However, in this case, the mounting space for the planar stack package may be increased, so that the planar stack package has no practical use. In addition, due to the limitation of the mounting space for the planar stack package, it may happen that fabrication of the planar stack package is impossible.